1. Field of the Invention
The invention is related to an integrated circuit (IC) chip, and more particularly to an integrated circuit chip having a seal ring, a ground ring and a guard ring.
2. Description of the Related Art
A semiconductor wafer comprises a number of integrated circuit chips formed through integrated circuit manufacturing process with each integrated circuit chip comprises a number of circuits, such as digital circuits, analog circuits and radio frequency (RF) circuits. A scribing line is formed between any two adjacent integrated circuit chips to facilitate the scribing of integrated circuit chips. When scribing the integrated circuit chip, the generated stress will cause damage to the circuits of the integrated circuit chip. Therefore, a seal ring is normally formed between the integrated circuit chip and the scribing line to prevent the integrated circuit chip from being damaged during the scribing process.
Refer to FIG. 1A and FIG. 1B. FIG. 1A is a top view of a conventional integrated circuit chip. FIG. 1B is a partial enlargement of a cross-sectional view of the integrated circuit chip along the cross-sectional line 1B-1B′ in FIG. 1A. In FIG. 1A and FIG. 1B, an integrated circuit chip 10 includes a silicon substrate 14, a digital circuit 12, an RF circuit 13, a seal ring 11, two input/output (I/O) pads 12a and 13a. The digital circuit 12, the RF circuit 13, the seal ring 11, the I/O pads 12a and 13a are formed on the silicon substrate 14. Of which, the I/O pads 12a and 13a are respectively electrically connected with the digital circuit 12 and the RF circuit 13. The seal ring 11 surrounds the integrated circuit chip 10 and encloses the digital circuit 12, the RF circuit 13, the I/O pads 12a and 13a. As shown in FIG. 1B, the seal ring 11 includes a P well 15, a P+ doping layer 16, three metal layers 17a˜17c, three dielectric layers 18a˜18c, three vias 19a˜19c, a passivation layer 18d, and a nitride layer 18e. The P well 15 is formed on the silicon substrate 14. The P+ doping layer 16 is formed in the P well 15 and the surface of the P+ doping layer 16 is co-planar with the surface of the P well 15. The dielectric layers 18a˜18c, the passivation layer 18d, and the nitride layer 18e are formed on the surface of the P well 15 and the surface of the P+ doping layer according to a bottom-up sequence. The metal layers 17a˜17c are respectively formed on the dielectric layers 18a˜18c and are respectively covered by the dielectric layers 18b, 18c and the passivation layer 18d. The vias 19a˜19c are respectively formed in the dielectric layers 18a˜18c. The via 19a is electrically connected with the P+ doping layer 16 and metal layer 17a. The via 19b is electrically connected with the metal layers 17a and 17b. The via 19c is electrically connected with the metal layer 17b and 17c. 
Since the seal ring 11 is a continuous ring structure, the digital circuit 12 is a circuit, which easily generates noises. Moreover, the RF circuit 13 is a circuit which is easily interrupted by the noise, so that the noise generated by the digital circuit 12 or the I/O pad 12a will be easily transmitted to the RF circuit 13 or the I/O pad 13a through the seal ring 11, resulting in noise coupling and further affecting the normal operation of the RF circuit 13.
Several conventional methods have been provided to resolve the noise-coupling problem disclosed above. Refer to FIG. 2A and FIG. 2B. FIG. 2A is a partial top view of an integrated circuit chip disclosed in U.S. Patent Publication No. U.S. 2003/0122235 A1. FIG. 2B is a partial enlargement of a cross-sectional view of the integrated circuit chip along the cross-sectional line 2B-2B′ in FIG. 2A. In FIG. 2A and FIG. 2B, an integrated circuit chip 20 includes a silicon substrate 25, an I/O pad 22 of a digital circuit, a ground pad 24, an RF circuit 23, two seal rings 21a and 21b. The I/O pad 22 of the digital circuit, the ground pad 24, the RF circuit 23, the seal rings 21a and 21b are formed on the silicon substrate 25. The seal rings 21a and 21b surround the integrated circuit chip 20 and enclose the I/O pad 22 of the digital circuit, the ground pad 24 and the RF circuit 23. The seal ring 21a and 21b are two discontinuous rings. The seal ring 21b is formed closer to the I/O pad 22 of the digital circuit, the ground pad 24 and the RF circuit 23 than the seal ring 21a is. To prevent the noise generated by the I/O pad 22 of the digital circuit from being transmitted to the RF circuit 23 through the seal rings 21a and 21b, the gaps of the seal rings 21a and 21b are alternately arranged. The I/O pad 22 of the digital circuit and the RF circuit 23 are formed corresponding to the seal ring 21a through the two gaps of the seal ring 21a. The ground pad 24 is formed near the seal ring 21b. 
The seal ring 21a and 21b have the same sectional structure, and the sectional structure of the seal ring 21b is exemplified herein. As shown in FIG. 2B, the seal ring 21b includes a N well 26, a P+ doping layer 27, a salicide layer 28, a shallow trench isolation (STI) layer 29, six dielectric layers 30a˜30f, six metal layers 34a˜34f, six contact layer 35a˜35f, a passivation layer 31, a nitride layer 32 and a polyimide (PI) layer 33. The N well 26 is formed on the silicon substrate 25. The P+ doping layer 27 and the STI layer 29 are formed in the N well 26. The surface of the P+ doping layer 27 and that of the STI layer 29 are co-planar with the surface of the N well 26. The STI layer 29 respectively enables the seal ring 21b and the I/O pad 22 of the digital circuit, the ground pad 24 and the RF circuit 23 to be electrically isolated from each other. The salicide layer 28 is formed in the P+ doping layer 27. The surface of the salicide layer 28 is co-planar with the surface of the P+ doping layer 27. The dielectric layers 30a˜30f, the passivation layer 31, the nitride layer 32 and the PI layer 33 are respectively formed on the surfaces of the N well 26, the salicide layer 28 and the STI layer 29 according to a bottom-up sequence. The metal layers 34a˜34f are respectively formed on the surfaces of the dielectric layers 30a˜30f and are respectively covered by the dielectric layers 30b˜30f and the passivation layer 31. The contact layers 35a˜35f are respectively formed in the dielectric layers 30a˜30f. The contact layer 35a is electrically connected the metal layer 34a and the salicide layer 28. The contact layers 35b˜35f are respectively electrically connected any two adjacent metal layers of the metal layers 34b˜34f according to a bottom-up sequence.
It is noteworthy that a PN junction is formed between the N well 26 and the silicon substrate 25, so the electric charges, which are generated during the process of manufacturing the seal rings 21a and 21b according to a plasma etching method, cannot be discharged through the silicon substrate 25 and will build up on the seal rings 21a and 21b, severely affecting the electrical characteristics of the integrated circuit chip 20. Moreover, the N well 26 formed underneath the gaps of the seal rings 21a and 21b is not cut off, so the noise generated by the I/O pad 22 of the digital circuit still can be transmitted to the RF circuit 23 through the N well 26, causing noise coupling to occur. Besides, the double ring design of the seal rings 21a and 21b will increase the size of the integrated circuit chip 20.
Refer to FIG. 3A and FIG. 3B. FIG. 3A is a partial top view of an integrated circuit chip disclosed in U.S. Pat. No. 6,492,716. FIG. 3B is a partial enlargement of a cross-sectional view of the integrated circuit chip along the cross-sectional line 3B-3B′ in FIG. 3A. In FIG. 3A and FIG. 3B, an integrated circuit chip 40 includes a P type silicon substrate 44, a digital circuit 42, an RF circuit 43 and a seal ring 41. The digital circuit 42, the RF circuit 43 and the seal ring 41 are formed on the P type silicon substrate 44. The seal ring 41 surrounds the integrated circuit chip 40 and encloses the digital circuit 42 and the RF circuit 43. The seal ring 41 is a discontinuous ring structure and has a number of gaps, two gaps for instance, such that part of the seal ring 41 is adjacent to the digital circuit 42 and another part of the seal ring 41 is adjacent to the RF circuit 43.
As shown in FIG. 3B, the seal ring 41 includes an N well 45, a salicide layer 46, a gate oxide 47, an STI layer 48, a polysilicon layer 49, six dielectric layers 50a˜50f, six metal layer 53a˜53f, six vias 54a˜54f, an oxide layer 51 and a nitride layer 52. The N well 45 and the STI layer 48 are formed on the P type silicon substrate 44. The salicide layer 46 is formed in the N well 45. The gate oxide 47 is formed in the salicide layer 46. The surface of the gate oxide 47 is co-planar with the surface of the STI layer 48. The dielectric layers 50a˜50f, the oxide layer 51 and the nitride layer 52 are respectively formed on the surfaces of the gate oxide 47 and the STI layer 48 according to a bottom-up sequence. The polysilicon layer 49 and the metal layers 53a˜53f are respectively formed on the dielectric layers 50a˜50f and are respectively covered by the dielectric layers 50b˜50f and the oxide layer 51. The contact layers 54a˜54f are respectively formed in the dielectric layers 50a˜50f. The contact layer 54a is electrically connected the metal layer 53a and the polysilicon layer 49. The contact layers 54b˜54f are respectively electrically connected any two adjacent metal layers of the metal layers 53b˜53f according to a bottom-up sequence.
Despite that the polysilicon layer 49 and the gate oxide 47 can reduce the noise coupling of the integrated circuit chip 40, the electric charges, which are generated during the process of manufacturing the seal ring 41 according to a plasma etching method, cannot be discharged through the P type silicon substrate 44 and will build up on the seal ring 41, severely affecting the electrical characteristics of the integrated circuit chip 40.